vSync Circuits: A complete solution for multiple clock domain design

vSync Circuits Ltd., founded in 2010 by industry veterans Dr. Reuven Dobkin, Leonid Brook, and Prof. Ran Ginosar, develops innovative technology for reliable integration and verification of multiple-clock domain SoCs, suitable for both ASICs and FPGAs. The company’s portfolio includes CDC, LINT and AXI-based integration tools and a comprehensive RTL IP library.

Synchronization failures are often intermittent and difficult to detect, leading to prolonged design cycles. The vSync Vincent CDC platform offers a comprehensive solution by providing foolproof synchronizers and static design verification. It identifies potential problems and evaluates reliability, ensuring a more efficient and dependable design process. The Vincent CDC platform comprises a suite of EDA tools and libraries that can be used independently or as part of an integrated design flow, seamlessly integrating into any ASIC or FPGA design process.

• vSync vGenerator: Generates synchronization IP cores, offering a range of reliable and verified synchronization solutions for various clock domain crossing (CDC) types and system requirements.
• vSync vChecker: Used for static CDC verification and management, enabling efficient identification, analysis, resolution, and reliability grading of CDC issues.
• vSync vTest: A regression test management tool employed during design sign-offs and for multiple-mode CDC analysis, ensuring comprehensive testing coverage.
• vSync RTL Libraries: Facilitate behavioural and gate-level CDC verification for multiple clock domain designs.

Together, these tools and libraries comprehensively address all integration and verification needs for designs involving multiple clock domains.

Additionally, the vSync Circuits portfolio includes the vSync vLinter tool, which provides comprehensive static rule-based design analysis for VHDL and Verilog/System-Verilog designs. vLinter detects and addresses design bugs caused by poor coding practices, such as unsynthesizable code, signal contention, unreachable FSM states, unintentional latches, undriven signals, race conditions, out-of-range indexing, incomplete case statements, and mismatches between simulation and synthesis. The tool features multiple predefined rule sets tailored to different applications, including avionics and space. Users can customize their rule policies for specific projects by selecting and modifying vLinter rules. The RTL design is analyzed based on the chosen rule policy, and any violations are reported for user review. vLinter shares its project database with vSync vChecker CDC, facilitating smooth transitions between LINT and CDC analysis.

Contact Information:

Reuven Dobkin

email: reuven@vsyncc.com

phone: +972-54-4248169

www.vsyncc.com